Charge Pump Using Gain-Boosting and Positive Feedback Techniques in 180-nm Digital CMOS Process

Alireza Ghorbani

Abstract


The charge pump (CP) circuit is an essential element in a delay-locked loop (DLL). This paper proposes a new CP using gain-boosting technique. Two possible solutions for gain-boosting circuit implementation are presented. One solution is based on common-source amplifier. In another solution, positive feedback method is employed at the output stage to increase the output resistance of the amplifier. Therefore, DC-gain of the amplifier is improved. In addition, nonlinear current mirror is employed in which the gain is dependent to the input current. To evaluate the performance of the proposed CPs, simulations are done in a 0.18 μm CMOS process with the supply voltage of 1.8 V. The simulation results indicate that the proposed CPs can obtain good current matching characteristics in the low power applications. The mismatch between up and down CP currents is less than 1%.

Keywords


Charge pump; Common-source amplifier; Gain-boosting; Positive feedback; Nonlinear current mirror.

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References


T. I. Badal , P. Maroofee , M. A. S. Bhuiyan , L. F. Rahman , M. B. I. Reaz , M. A. Mukit, “Low power delay locked-loop using 0.13μm CMOS technology,”, International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), pp. 176-179, 2016.

Chi-Nan Chuang, Shen-Iuan Liu, “A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump,”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, Issue: 11, pp. 939 – 943, 2007.

Muhammad AbrarAkram, Myeong-Ho Lee, Dong-Hyeok Cho, In-Chul Hwang, “A 0.012mm2, 0.96-mW All-Digital Multiplying Delay-Locked Loop Based Frequency Synthesizer for GPS-L4 band,”, IEEE International Conference on Consumer Electronics (ICCE), pp. 1-2, 2020.

Sami Ur Rehman, Mohammad Mahdi Khafaji, Ali Ferschischi; Corrado Carta, Frank Ellinger, “A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS,”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, Issue: 5, pp. 806 – 810, 2020.

MyeongjoJeong, Minchul Shin, Jinwoo Kim; ManhoSeung, Seokkiu Lee, Jingook Kim, “Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop,”, IEEE Transactions on Electromagnetic Compatibility, Vol. 62, Issue: 5, pp. 1840 – 1851, 2020.

Yuan Sun, Liter Siek, Pengyu Song, “Design of a High Performance Charge Pump Circuit for Low Voltage Phase-locked Loops,”, IEEE ISle. Singapore, pp. 271-274, 2007.

Hwang M S, Kim J, Jeong D K, “Reduction of pump current mismatch in charge-pump PLL,”, Electronics Letters. vol. 45, pp. 135-136, 2009.

Shuangshuang Zheng, Zhiqun Li, “A novel COMS Charge Pump with high performance for phase-locked loops synthesizer,”, IEEE ICCT. Jinan, pp. 1062-1065, 2011.

Ngo TrongHieu, Tae-Woo Lee, Hyo-Hoon Park, “A perfectly Current Matched Charge Pump of CP-PLL for Chip-to-Chip Optical Link,”, CLEO. Seoul, pp. 1-2, 2007.

JiaYaoyao, Fang Jian, Qiao Ming, Zhou Zekun, Yang Wentao, Zhang Bo, “A charge pump with reduced current variation and mismatch in low-voltage low-power PLLs,”, IEEE International Conference of Electron Devices and Solid-state Circuits, pp. 1-2, 2013.

Kashyap K. Patel, Nilesh D. Patel and Kruti P. Thakore, “Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18 um CMOS Technology”, IOSR Journal of VLSI

and Signal Processing (IOSR-JVSP) Vol. 2, Issue 4, pp. 21-25, 2013.

J. Keller "SB-1250: A high performance power efficient chip multiprocessor (CMP) targeting networking applications" Microprocessor Forum 2000

C.M. Hung, K.O. Kenneth, "A Fully Integrated 1.5 V 5.5 GHz CMOS Phase Locked Loop", IEEE Journal Of Solid State Circuits, Vol. 37, Pp. 521-525, April 2002.

Behrouj, A., Ghorbani, A., Ghaznavi-Ghoushchi, M., and Jalali, M.: ‘A Low-Power CMOS Transceiver in 130 nm for Wireless Sensor Network Applications’, Wireless Personal Communications, 2019, 106, (3), pp. 1015-1039.

R. A. Baki and M. N. El-Gamal, “A new CMOS charge pump for low voltage (1V) high speed PLL Applications” Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium, Vol. 1, pp. 657-660, 2003.

Jae-Shin Lee, Min-Sun Keel, Shin-II Lim, et al. "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Letters. vol. 36, pp. 1907-1908,2000.

Soleiman E, Kamarei M, "New low current mismatch and wide output dynamic range charge pump," IEEE ICEE. Tehran, Iran, pp. 1-5, 2011.

NoushinGhaderi, Ali Dehghani, “A novel high swing, low power charge pump circuit with excellent current matching”, 24th Iranian Conference on Electrical Engineering (ICEE), pp. 1797-1800, 2016.

Rania H. Mekky, Mohamed Dessouky, “Design of a Low-Mismatch Gain-Boosting Charge Pump for Phase-Locked Loops”, International Conference on Microelectronics, pp. 1-4, 2007.

J. Shin, I.-Y. Chung, Y. J. Park et H. S. Min, “A new charge pump without degradation in threshold voltage due to body effect [memory applications],” IEEE Journal of Solid-State Circuits, vol. 35, n° %18, pp. 1227-1230, August 2000.

K. H. Choi, J. M. Park, J. K. Kim, T. S. Jung et K. D. Suh, “Floating-well charge-pump circuits for sub-2.0-V single power supply flash memories,” chez Symposium VLSI circuits Dig. Tech. Papers, 1997.

G. Palumbo, D. Pappalardo et M. Gaibotti, “Charge-Pump Circuits: Power-Consumption Optimization,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and applications, vol. 49, n° %111, pp.1535-1542, November 2002.

C. Lauterbach, W. Weber et D. Romer, “Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 719-723, May 2000.

S. Ngueya W., J. Mellier, S. Ricard, J. M. Portal et H. Aziza, “Ultra Low Power Charge Pump with Multi-Step Charging and Charge Sharing,” chez IEEE 8th International Memory Workshop (IMW), Paris, 2016.

A.R. Ghorbani, M.B. Ghaznavi-Ghoushchi, A novel transceiver structure including power and audio amplifiers for Internet of Things applications,Computers & Electrical Engineering, Volume 62,Pages 29-43 ,2017.

S. M. Anisheh, H. Abbasizadeh, H. Shamsi, C. Dadkhah, K. Y. Lee, “A 84 dB DC-Gain Two-Stage Class-AB OTA,” IET Circuits Devices & Systems, pp. 1-10, 2019.

J. A. Galan, A. J. López-Martín, R. G. Carvajal, J. Ramírez-Angulo, and C. Rubia-Marcos, “Super class-AB OTAs with adaptive biasing and dynamic output current scaling,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 3, pp. 449-457, 2007.

Johns, D., Martin, K.: ‘Analog integrated circuit design’‚ JohnWiley& Sons, 1997.

R. S. Assaad, and J. Silva-Martinez, “The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, 2009.

Y.L. Li, K.F. Han, X. Tan, N. Yan and H. Min, “Transconductance enhancement method for operational transconductance amplifiers,” Electron. Lett., vol. 46, no. 19, pp. 1321–1323, 2010.




DOI: https://doi.org/10.33180/InfMIDEM2022.105

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