Area efficient CORDIC Accelerator for Embedded Processor Datapaths

Abstract

A proven approach to enhance the performance of an embedded processor is to add specialized hardware accelerator blocks. We present two novel architectures for a CORDIC accelerator based on mixed hardware-software approach. These CORDIC accelerators can be integrated with an embedded processor datapath and we investigate the processor performance in terms of execution time and energy efficiency. The first accelerator design is based on the Standard CORDIC algorithm. The Standard CORDIC based accelerated embedded processor datapath is 35% more cycle efficient than a datapath lacking Standard CORDIC accelerator, leading to 34% energy reduction. This mixed hardware-software implementation of Standard CORDIC algorithm is area efficient when compared to hardware only implementation which resulted in saving one addition/subtraction block. The second accelerator design is based on a Modified CORDIC algorithm. Our evaluation shows that a Modified CORDIC accelerated embedded processor datapath is 14.5X times more cycle efficient than a datapath lacking Modified CORDIC accelerator, leading to 14X times energy reduction with a very small area overhead. The mixed hardware-software Modified CORDIC accelerator is area efficient when compared to hardware only implementation which resulted in saving four multipliers and two adders.