Design of Fault-Tolerant Reversible Floating Point Division

Kamaraj A, Marichamy P

Abstract


Nowadays, power dissipation and the size of the computational devices are playing a major role in semiconductor industry. The size of a transistor limits the scaling of the semiconductor devices. In turn, an alternative technology is a reversible logic based computational devices. In this paper, new reversible KMD gates capable of producing many logical functions are proposed. The proposed gates satisfy the fundamental properties of reversible logic, reversibility & universality. The functionality of the gates is verified in Quantum Cellular Automata (QCA), which is popular for validating reversible logic. In addition, the proposed gates are fault-tolerant as it is having parity preservation. An N-bit fault-tolerant reversible floating point division unit (FTRFPD) is designed to the IEEE 754 single precision standard using the above fault-tolerant reversible gates. It has parallel adder, latch, multiplexer, shift register, rounding and normalization register. All the functional blocks are fault-tolerant in nature since they are constructed from the FT Gates. The FTRFPD is capable of dividing two numbers using the procedural algorithm. The QCA based simulation results confirm that the designed unit is having improved Quantum Cost of 9.85%, 29.63% of Delay and 33.54 % Number of Gates over the existing designs.


Keywords


Reversible Logic; Quantum Cost; Delay; Garbage Outputs

Full Text:

PDF

References


. R. Landauer, “Irreversibility and heat generation in the computing process”, IBM J. Research and Development, Vol. 5(3), July 1961, pp:183-191.

. C.H.Bennett, “Logical reversibility of computation”, IBM J. Research and Development, Vol. 17, November1973,pp:525 – 532.

. Chris Thachuk, “Logically and Physically Reversible Natural Computing”: Proc. 5th International Conference on Reversible Computation (RC'13), Vol. 7948,2013, pp. 247–262.

. Behrooz Parhami, “Fault-Tolerant Reversible Circuits”, Proc. 40th Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, October 2006, pp. 1726–1729.

. K. Sridharan, Vikramkumar Pudi, “Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology”, Studies in Computational Intelligence, Springer, Vol. 599, 2015.

. Craig S Lent, Mo Liu and Yuhui Lu, “Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling”, Nanotechnology, Vol. 17, 2006, pp.4240-4251.

. Biswas, Md.Mahmudul Hasan, Chowdhury, Md.Hasan Babu, “Efficient approaches for designing reversible Binary Coded Decimal adders”, Microelectronics Journal, Vol. 39, 2008, pp. 1693–1703.

. Hafiz Md. HasanBabu, Md. Solaiman Mia, “Design of a compact reversible fault tolerant division circuit”, Microelectronics Journal, Vol. 51, 2016, pp.:15–29.

. T. Toffoli,“Reversible Computing”, Technical Report MIT/LCS/TM-151, 1980, pp. 1-37.

. E. Fredkin, T. Toffoli, “Conservative logic”, Int. J. Theor. Phys., Vol. 21,1980, pp.219–253.

. A. Peres, “Reversible logic and quantum computers”, Phys. Rev., Vol. 32, 1985, pp. 3266–3276.

. R. Feynman, “Quantum mechanical computers”, Found. Phys., Vol. 16 (6), 1986, pp. 11-20.

. Papiya Biswas, Namit Gupta, Nilesh Patidar, “Basic Reversible Logic Gates and It’s QCA Implementation”, Int. Journal of Engineering Research and Applications, Vol. 4 (6), June 2014, pp.12-16.

. Ali NewazBahar, SajjadWaheed, NazirHossain, “A new approach of presenting reversible logic gate in nano-scale”, DOI 10.1186/s40064-015-0928-4, Springer, 2015.

. Kalyan S. Perumalla, “Introduction to Reversible Computing”, CRC Press, 2014.

. Kamaraj, A., P.Marichamy, S.Karthika Devi, and M.Nagalakshmisubraja. “Design and Implementation of Adders using Novel Reversible Gates in Quantum Cellular Automata”, Indian Journal of Science and Technology, Vol 9(8), 2017, pp. 1-7.

. MD. SaifulIslam, Zerina Begum, “Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder”, Journal of Bangladesh Academy of Sciences, Vol. 32 (2), 2008, pp.243-249.

. Sen, Ganeriwal, Sikdar, “Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA”, Hindawi, dx.doi.org/10.1155/2013/850267, May 2013, 9 pages.

. Valinataj, Mirshekar, Hamid Jazayeri, “Novel low-cost and fault-tolerant reversible logic adders”, Computers and Electrical Engineering, Vol. 53, 2016, pp.56–72.

. Md. Riazur Rahman, “Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis”, International Journal of Computer Applications, Vol. 108 (2), December 2014, pp. 7-12.

. Xuemei, Fulong, Liangmin, Yonglong, Min Hu, “Design of fast fault tolerant reversible signed multiplier”, International Journal of the Physical Sciences, Vol. 7(17), 23 April 2012, pp. 2506 - 2514.

. A.V. Anantha Lakshmi, Gnanou Florence Sudha, “Design of a reversible floating-point square root using modified non-restoring algorithm”, Microprocessors and MicrosystemsVol. 50, 2017, pp. 39–53.

. Belayet Ali, Mosharof Hossin, Eneyat Ullah, “Design of Reversible Sequential Circuit Using Reversible Logic Synthesis”, International Journal of VLSI design & Communication Systems (VLSICS) Vol.2 (4), December 2011, pp. 37- 45.

. Thapliyal H,Vinod A.P., “Design of reversible sequential elements with the feasibility of transistor implementation”, In Proceedings of the IEEE International Symposium on Circuits and Systems, 2007,pp. 625–628.

. Faraz Dastan, Majid Haghparast, “A novel nanometric fault tolerant reversible divider”, International Journal of the Physical Sciences Vol. 6(24), 16 October 2011, pp. 5671-5681.

. L.Jamal, H.M.H.Babu, “Efficient approaches to design a reversible floating point divider”, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, Vol. 13, 2013, pp.3004–3007.

. IEEE standard for floating-point arithmetic, IEEE Std.754-2008, 2008, pp.1–58.

. Carl Hamacher, Vranesic, Safwat Zaky, “Computer Organization”, 5th Edition, Tata McGraw-Hill, 2011.


Refbacks



Copyright (c) 2018 Informacije MIDEM