Power and Area Efficient Sense Amplifier Based Flip Flop with Wide Voltage and Temperature Upholding for Portable IoT Applications
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M. A. S. Bhuiyan, “CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices,” Informacije MIDEM, vol. 50, no. 2, pp. 105–114, Sep. 2020, doi: 10.33180/InfMIDEM2020.203.
M. Arunraja, V. Malathi, and E. Sakthivel, “Distributed Energy Efficient Clustering Algorithm for Wireless Sensor Networks,” Informacije MIDEM, vol. 45, no. 3, pp. 180–187, 2015.
S. Raj and S. S. Ramapackiam, “Energy Efficient and Low dynamic power Consumption TCAM on FPGA,” Informacije MIDEM, vol. 51, no. 3, Nov. 2022, doi: 10.33180/InfMIDEM2022.304.
O. A. Shah, I. Ahmed Khan, G. Nijhawan, and I. Garg, “Low Transistor Count Storage Elements and their Performance Comparison,” in 2018 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN), Greater Noida (UP), India, Oct. 2018, pp. 801–805. doi: 10.1109/ICACCCN.2018.8748364.
H. You, J. Yuan, W. Tang, Z. Yu, and S. Qiao, “A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS,” Electronics, vol. 9, no. 5, p. 802, May 2020, doi: 10.3390/electronics9050802.
I. A. Khan, O. A. Shah, and M. T. Beg, “Analysis of different techniques for low power Single Edge Triggered Flip Flops,” in 2011 World Congress on Information and Communication Technologies, Mumbai, India, Dec. 2011, pp. 1363–1367. doi: 10.1109/WICT.2011.6141447.
Y. Lee, G. Shin, and Y. Lee, “A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications,” IEEE Access, vol. 8, pp. 40232–40245, 2020, doi: 10.1109/ACCESS.2020.2976773.
D. Pan, C. Ma, L. Cheng, and H. Min, “A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications,” IEEE Trans. VLSI Syst., vol. 28, no. 1, pp. 243–251, Jan. 2020, doi: 10.1109/TVLSI.2019.2934899.
A. Karimi, A. Rezai, and M. M. Hajhashemkhani, “A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power,” Integration, vol. 60, pp. 160–166, Jan. 2018, doi: 10.1016/j.vlsi.2017.09.002.
O. A. Shah, G. Nijhawan, and I. A. Khan, “Low power area efficient self-gated flip flop: Design, implementation and analysis in emerging devices,” Engineering and Applied Science Research, vol. 49, p. 744752, 2022, doi: 10.14456/EASR.2022.72.
J. Lin, Y. Hwang, C. Wong, and M. Sheu, “Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems,” Electron. lett., vol. 51, no. 1, pp. 20–21, Jan. 2015, doi: 10.1049/el.2014.3922.
S. Lapshev and S. M. R. Hasan, “New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements,” IEEE Trans. Circuits Syst. I, vol. 63, no. 10, pp. 1673–1681, Oct. 2016, doi: 10.1109/TCSI.2016.2587282.
O. A. Shah, G. Nijhawan, and I. A. Khan, “Improved Sense Amplifier Based Flip Flop Design For Low Power And High Data Activity Circuits,” Journal of Applied Science and Engineering, vol. 26, no. 7, pp. 1047–1053, Oct. 2022, doi: 10.6180/jase.202307_26(7).0015.
A. Ramaswami Palaniappan and L. Siek, “Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop,” Electron. lett., vol. 54, no. 15, pp. 938–939, Jul. 2018, doi: 10.1049/el.2018.1134.
A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, “A novel high-speed sense-amplifier-based flip-flop,” IEEE Trans. VLSI Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005, doi: 10.1109/TVLSI.2005.859586.
H. Jeong, T. W. Oh, S. C. Song, and S.-O. Jung, “Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation,” IEEE Trans. VLSI Syst., vol. 26, no. 4, pp. 609–620, Apr. 2018, doi: 10.1109/TVLSI.2017.2777788.
B. Nikolic, V. G. Oklobdzija, V. Stojanovic, Wenyan Jia, James Kar-Shing Chiu, and M. Ming-Tak Leung, “Improved sense-amplifier-based flip-flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884, Jun. 2000, doi: 10.1109/4.845191.
J.-C. Kim, Y.-C. Jang, and H.-J. Park, “CMOS sense amplifier-based flip-flop with two N-C2MOS output latches,” Electron. Lett., vol. 36, no. 6, p. 498, 2000, doi: 10.1049/el:20000409.
“Predictive Technology Model,” PTM. https://ptm.asu.edu (accessed Oct. 10, 2022).
DOI: https://doi.org/10.33180/InfMIDEM2023.104
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